1. Field of the Invention
The present invention relates to an AD conversion circuit and a solid-state image pickup device including the AD conversion circuit.
Priority is claimed on Japanese Patent Application No. 2012-222044, filed Oct. 4, 2012, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
As an example of a solid-state image pickup device using a tdcSS (=time to digital converter Single Slope) type AD conversion circuit obtained by combining a TDC (=Time to Digital Converter) type AD conversion circuit with an SS (=Single Slope) type AD conversion circuit (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2006-340044), a configuration disclosed in Japanese Unexamined Patent Application, First Publication No. 2008-92091 has been known. FIG. 18 illustrates the configuration of the tdcSS type AD conversion circuit in accordance with the related art. First, the configuration and the operation of the tdcSS type AD conversion circuit of FIG. 18 will be described.
The tdcSS type AD conversion circuit illustrated in FIG. 18 includes a clock generation unit 1030, a comparison unit 1031, a latch unit 1033, a counting unit 1034, and a reference signal generation unit 1035. The clock generation unit 1030 has a delay circuit including 8 delay units DU[0] to DU[7]. The comparison unit 1031 has a comparison circuit CMP that compares an analog signal Signal to be subjected to AD conversion with a ramp wave Ramp that decreases with the passage of time. In the comparison unit 1031, a time interval (the magnitude in a time axis direction) corresponding to the magnitude of the analog signal Signal is generated.
The latch unit 1033 has latch circuits L—0 to L—7 that latch the logical states of output clocks CK[0] to CK[7] of the delay units DU[0] to DU[7] constituting the clock generation unit 1030. The counting unit 1034 has a counter circuit CNT that counts the output clock CK[7], which is output through the latch circuit L—7 of the latch unit 1033, as a counting clock. A control signal RST input to the counting unit 1034 is a signal for resetting the counter circuit CNT. The reference signal generation unit 1035 generates the ramp wave Ramp that is a reference signal. Comparison output C0 of the comparison unit 1031 is input to a buffer circuit BUF2. The buffer circuit BUF2 is an inversion buffer circuit that inverts the comparison output C0 of the comparison unit 1031 and outputs a control signal Hold.
The latch circuits L—0 to L—7 constituting the latch unit 1033 are in an enable (valid, active) state when the control signal Hold output from the buffer circuit BUF2 is High, and output the output clocks CK[0] to CK[7] of the delay units DU[0] to DU[7] without change. Furthermore, the latch circuits L—0 to L—7 enter a disable (invalid, holding) state when the control signal Hold is transitioned from High to Low, and latch logical states corresponding to the output clocks CK[0] to CK[7] of the delay units DU[0] to DU[7] at that time.
Next, an operation of the related art will be described. FIG. 19 illustrates the operation of the A/D conversion circuit in accordance with the related art.
First, at a timing according to the comparison start in the comparison unit 1031, as a start pulse (=StartP), a clock of a cycle which approximately coincides with the delay time (the sum of delay times of the 8 delay units DU[0] to DU[7]) of the clock generation unit 1030 is input to the clock generation unit 1030. In this way, the delay units DU[0] to DU[7] of the clock generation unit 1030 start to operate. The delay unit DU[0] constituting the clock generation unit 1030 delays the start pulse StartP and outputs the output clock CK[0], and the delay units DU[1] to DU[7] constituting the clock generation unit 1030 delay output signals of delay units of a previous stage and output the output clocks CK[1] to CK[7], respectively. The output clocks CK[0] to CK[7] of the delay units DU[0] to DU[7] are input to the latch circuits L—0 to L—7 of the latch unit 1033. The latch circuit L—7 outputs the received output clock CK[7] of the delay unit DU[7] to the counting unit 1034 without change.
The counting unit 1034 performs a counting operation based on the output clock CK[7]. In this counting operation, a count value increases or decreases with the rise or fall of the output clock CK[7]. At a timing (a second timing) at which the analog signal Signal approximately coincides with the ramp wave Ramp, the comparison output C0 of the comparison unit 1031 is inverted. Moreover, at a timing (a first timing) after the comparison output C0 is buffered in the buffer circuit BUF2, the control signal Hold is Low.
In this way, the latch circuits L—0 to L—7 of the latch unit 1033 enter a disable (holding) state. At this time, logical states corresponding to the output clocks CK[0] to CK[7] of the delay units DU[0] to DU[7] are latched in the latch circuits L—0 to L—7. The counting unit 1034 latches a count value when the latch circuit L—7 stops operating. According to the logical state latched in the latch unit 1033 and the count value latched in the counting unit 1034, digital data corresponding to the analog signal Signal is obtained.
According to Japanese Unexamined Patent Application, First Publication No. 2012-39386, a latch control unit is provided to control the operation of the latch unit 1033, to allow the latch circuits L—0 to L—6 of the latch unit 1033 to be in an enable (active) state at the second timing, and to allow the latch circuits L—0 to L—7 of the latch unit 1033 to be in a disable (hold) state at the first timing, thereby shortening the operation period of the latch circuits L—0 to L—6 of the latch unit 1033, resulting in the achievement of low current consumption of the tdcSS type AD conversion circuit. The latch control unit has an inversion delay circuit that inverts and delays the comparison output C0 of the comparison unit 1031 in order to generate the time difference between the second timing and the first timing.
In the conventional tdcSS type AD conversion circuit and a solid-state image pickup device using the same, AD conversion accuracy is likely to deteriorate due to bounce of power and ground.
In a column circuit provided in the image pickup device using the conventional tdcSS type AD conversion circuit, the comparison unit 1031, the latch unit 1033, and the counting unit 1034 are arranged for each column in correspondence with each column of pixels arranged in a matrix form. A power supply voltage VDD is supplied to each part of the column circuit. However, the closer a column is to the center (that is, the farther it is from the power), compared to a column at the end of the column circuit, since wiring resistance becomes larger, the larger voltage drop occurs, resulting in the reduction of the power supply voltage VDD. Furthermore, as a current consumed in the circuit becomes large, voltage drop becomes larger. For the same reason, the closer a column is to the center (that is, the farther it is from the ground), compared to a column at the end of the column circuit, the more the ground voltage GND increases. For example, in a column at the end of the column circuit, even when the power supply voltage VDD is 1.5 [V] and the ground voltage GND is 0 [V], there is a case in which the power supply voltage VDD is about 1.2 [V] and the ground voltage GND is about 0.3 [V] in the center column of the column circuit.
During an AD conversion period (for example, during an AD conversion period of a reset level that is approximately constant in all pixels), since the comparison outputs C0 of the comparison units 1031 of all columns are inverted almost at the same time, there is a case in which the latch control unit and the latch circuits L—0 to L—6 start to operate almost at the same time (enter an enable state). In this case, since a transient current flows through the latch control units and the latch circuits L—0 to L—6 of all columns, transient bounce (ringing of a transient voltage about the power supply voltage VDD of 1.2 [V] and the ground voltage GND of 0.3 [V]) of power and ground occurs in the vicinity of the center column of the column circuit due to the transient current and the wiring resistance.
In the conventional tdcSS type AD conversion circuit, at the timing after a delay time in the inversion delay circuit of the latch control unit from the timing at which the latch circuits L—0 to L—6 have started to operate almost at the same time, the latch circuits L—0 to L—6 enter a disable state to latch logical states of input signals. However, in the vicinity of the center column of the column circuit, since the delay time of the inversion delay circuit of the latch control unit varies in response to the power supply and ground voltages (the magnitude of bounce) and thus a latch timing varies, the latch circuits L—0 to L—6 are likely unable to precisely latch the logical states of the input signals. This event may occur frequently when the comparison output C0 of a plurality of comparison units 1031 are changed almost at the same time, so that the AD conversion accuracy is likely to deteriorate.